首页>
外国专利>
Combinational logic circuit, system and method for eliminating both positive and negative glitches
Combinational logic circuit, system and method for eliminating both positive and negative glitches
展开▼
机译:消除正毛刺和负毛刺的组合逻辑电路,系统和方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
A host adapter of a computer system includes combinational logic circuit eliminating both positive and negative-glitches from an input signal. The circuit comprises two NAND gates and two delay elements in one embodiment. The delay introduced by second delay element is twice that of the first delay element. The first delay element receives as input the input signal. The first NAND gate receives as inputs the input signal and the output of the first delay element. The second delay element receives as input the output of the first NAND gate. The second NAND gate receives as inputs the output of the first NAND gate and the output of the second delay element. The output of the second NAND gate comprises the input signal with both positive and negative glitches having a duration of less than the delay of the first delay element eliminated. In a second embodiment, the two NAND gates are replaced by two NOR gates.
展开▼