Apparatus and method for reducing read miss latency by predicting sequential instruction read-aheads

摘要

An apparatus and method for reducing the time required to supply a processor core with instructions uses a cache memory, a cache controller, and an instruction predecoding unit. When a line of instructions is retrieved into the cache memory, the instruction predecoding unit inspects the instructions in the line to determine if the line contains any nonsequential instructions. The cache controller stores an indication of whether the line contains nonsequential instructions with the line of instructions in the cache memory. If a given line of instructions does not contain any nonsequential instructions, the line of instructions following the given line is retrieved into the cache memory when one of the instructions in the given line is requested by the processor core.