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Pipelined microprocessor that pipelines memory requests to an external memory
Pipelined microprocessor that pipelines memory requests to an external memory
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机译:流水线微处理器,将内存请求流水到外部存储器
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摘要
Memory requests are pipelined to an external memory by forming a memory address during the same clock cycle that the associated instruction is executed, issuing a ready signal during the clock cycle that precedes the clock cycle in which information is output from an external memory, and directing information received from the external memory to a register file during the same clock cycle that the information is received. In addition, when an instruction requires the information that was requested by the previous instruction, the information is directed to an arithmetic logic unit (ALU) during the same clock cycle that the information is received. As a result, the cycle time required to retrieve information stored in a DRAM can be substantially reduced.
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