Method for reducing display locking in digital oscilloscopes or logic analyzers using inter-acquisition dithering techniques

摘要

In a test instrument, display locking is reduced by the addition of a non-constant time delay to each acquisition cycle. The time delay may be randomly chosen or follow a predetermined algorithm. Decreased system throughput caused by the addition of a non-constant time delay may be minimized by alternately storing acquired data in two acquisition memories. Display locking may also be reduced by rejecting selected triggers. The data acquired from these selected triggers is not processed for display. The triggers whose data is not processed for display may be randomly chosen or they may be chosen by a predetermined algorithm. Rejecting triggers and the addition of a non-constant time delay may be used in combination or individually to reduce display locking.