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Programmable high performance mode for multi-way associative cache/memory designs
Programmable high performance mode for multi-way associative cache/memory designs
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机译:用于多路关联高速缓存/内存设计的可编程高性能模式
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摘要
The present invention provides circuitry which facilitates user selection of alternative memory accessing techniques. The present invention provides a design approach or technique to transform the time associated with waiting for a valid "way-select" signal into cycle reduction time, thus providing a beneficial increase in the overall performance of multi-way associative cache and memory designs.
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