Hybrid-synchronous type clock synchronizing apparatus of which dominant gain greater than sum of other gains network therewith, and clock synchronizing method thereof

摘要

A clock synchronizing apparatus is constructed of a multi- input PLL circuit. The multi-input PLL circuit comprises a phase comparator, a variable frequency oscillator, a loop filter, and an adding device. The phase comparator includes a plurality of subtracting devices for subtracting an output signal from each of input signals and a plurality of amplifiers for obtaining a phase comparison characteristic corresponding to the output signal of each subtracting device and for amplifying each phase comparison characteristic by a predetermined gain. Each gain is predetermined for each input signal. One dominant gain is greater than the sum of the other gains.