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Computer system and method of allocating cache memories in a multilevel cache hierarchy utilizing a locality hint within an instruction

机译:利用指令内的局部性提示在多级缓存层次结构中分配缓存的计算机系统和方法

摘要

A computer system and method in which allocation of a cache memory is managed by utilizing a locality hint value included within an instruction. When a processor accesses a memory for transfer of data between the processor and the memory, that access can be allocated or not allocated in the cache memory. The locality hint included within the instruction controls if the cache allocation is to be made. When a plurality of cache memories are present, they are arranged into a cache hierarchy and a locality value is assigned to each level of the cache hierarchy where allocation control is desired. The locality hint may be used to identify a lowest level where management of cache avocation is desired and cache memory is allocated at that level and any higher level(s). The locality hint value is based on spatial and/or temporal locality for the data associated with the access. Data is recognized at each cache hierarchy level depending on the attributes associated with the data at a particular level. If the locality hint identifies a particular access for data as temporal or non-temporal with respect to a particular cache level, the particular access may be determined to be temporal or non-temporal with respect to the higher and lower cache levels.
机译:一种计算机系统和方法,其中通过利用指令中包括的局部性提示值来管理高速缓冲存储器的分配。当处理器访问内存以在处理器和内存之间传输数据时,可以在高速缓存中分配或不分配该访问。指令中包含的位置提示控制是否要进行高速缓存分配。当存在多个高速缓冲存储器时,将它们布置在高速缓存层次结构中,并将局部性值分配给需要分配控制的高速缓存层次结构的每个级别。局部性提示可以用于标识期望管理高速缓存激活并且在该级别以及任何更高级别分配高速缓存存储器的最低级别。位置提示值基于与访问相关联的数据的空间和/或时间位置。根据与特定级别的数据相关联的属性,在每个缓存层次结构级别识别数据。如果位置提示将对数据的特定访问相对于特定高速缓存级别识别为时间或非时间,则可以将特定访问确定为相对于较高和较低高速缓存级别是时间或非时间的。

著录项

  • 公开/公告号US5829025A

    专利类型

  • 公开/公告日1998-10-27

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US19960767950

  • 发明设计人 MILLIND MITTAL;

    申请日1996-12-17

  • 分类号G06F13/00;G06F12/12;

  • 国家 US

  • 入库时间 2022-08-22 02:38:16

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