METHOD FOR GENERATING TEST SEQUENCE FOR COMPRESSED SET

摘要

PROBLEM TO BE SOLVED: To generate a set of compressed sequence by generating a first test sequence which defines a necessary test input value to detect an objective failure selected from a failure list of an integrated circuit and an additional test sequence which defines a test input value from a failure list different from the detected one, judging whether or not a compression process is allowed, and repeating the compression process. ;SOLUTION: A failure list of an integrated circuit chip is defined and a test vector is generated for each failure. Whether a test vector set is present or not is judged. When the test vector set is not present, the test vector is defined to form a set. When the test vector set is actually present, whether or not the generated test vector can be compressed with an optional vector at the test set. If the test vector cannot be compressed, the generated test vector is added to a new set of test vectors. If the test vector can be compressed, the newly generated test vector is compressed with an existing vector in the test set, when the system returns to the generation for a next test vector. The process is repeated until a set of test vectors is generated.;COPYRIGHT: (C)1999,JPO