(57) Abstract It is while circuit designing, technique in order to choose the flip-flop of the optimum group which it should convert to BIST element is disclosed. This holds down the degradation in efficiency which is brought from that kind of conversion to minimum. If you follow this invention, while circuit designing the addition timing delay which is brought as the result of each conversion to BIST element of flip-flop those is installed while choosing the flip-flop which it should convert, because of this, is thought that only conversion possible flip-flop, is ideal in conversion, without bringing timing disturbance as the result. All logical cycles inside the circuit are divided, these ideal the smallest group of flip-flop, after that, is chosen for BIST conversion. Therefore, as for the choice technique which you follow this invention, while holding down augmentation of the silicon area which originates in BIST conversion to minimum it converts the fault cover maximally not only, it can hold down degradation in efficiency to minimum.
展开▼
