ESTIMATION METHOD FOR FAILURE PART IN SEQUENTIAL CIRCUIT AND CANDIDATE EXTRACTION IN ESTIMATION OF FAILURE PART AS WELL AS METHOD AND APPARATUS FOR WEIGHTING THEREOF

摘要

PROBLEM TO BE SOLVED: To obtain an estimation method in which the failure of a sequential circuit at the inside of an LSI is estimated by a method wherein a circuit extraction is performed in both an input direction and an output direction from a fail pin, a simulation by a multiple failure propagation assumption in the input boundary of a combination circuit is compared with an actual fail, a failure propagation value is estimated and an estimation value with reference to every fail vector is found. ;SOLUTION: A circuit extraction is performed to an input direction from an output terminal which is estimated to be the failure output of an LSI or which is estimated to be already a failure, and the circuit extraction is finished when it reaches an ininput terminal or to the output terminal of a flip-flop(F-F). Then, the input terminal of the obtained LSI or the output terminal of the F-F is used, a circuit extraction to an output direction is performed, and the output terminal of the LSI or the input terminal of the F-F is obtained. In addition, a sequential circuit is extracted to the input direction, and a combination circuit is obtained. A combination-circuit-input-terminal-state estimation #1 is an output estimation means which is used when a failure does not exist inside the circuit. An input-terminal-state estimation #2 and an input-terminal-state estimation #3 are procedures which are used to find an estimated failure part and a combination-circuit-input-terminal-state estimation value when it is assumed that the failure exists.;COPYRIGHT: (C)1999,JPO