首页> 外国专利> INTERRUPTION MULTIPLEX CIRCUIT AND INTERRUPTION MULTIPLEX SYSTEM

INTERRUPTION MULTIPLEX CIRCUIT AND INTERRUPTION MULTIPLEX SYSTEM

机译:中断多重电路和中断多重系统

摘要

PROBLEM TO BE SOLVED: To accelerate an interruption processing and to accelerate the entire system by selectively outputting the start address of the interruption processing to a CPU corresponding to an interruption request. ;SOLUTION: In this interruption multiplex circuit 5 for informing the interruption requests by one signal line relating to the plural interruption requests, a priority judgement part 6 outputs signals for indicating the interruption request of highest priority among the inputted interruption requests corresponding to the prescribed priority set beforehand when the plural interruption requests are simultaneously inputted. In an address register 7, so as to make the start addresses of the plural interruption processings correspond to the plural interruption requests inputtable to the priority judgement part 6, positions 71-7n for storing the respective start addresses are decided beforehand. A selector 8 selectively outputs the address present at the position storing the start address of the corresponding interruption processing to a data buffer 9 based on the signals for indicating one of the interruption requests from the priority judgement part 6.;COPYRIGHT: (C)1998,JPO
机译:解决的问题:通过选择性地将中断处理的开始地址输出到与中断请求相对应的CPU,来加速中断处理并加速整个系统。 ;解决方案:在该中断多路复用电路5中,通过一条信号线通知与多个中断请求有关的中断请求,优先级判断部分6输出用于指示输入的,与规定优先级相对应的中断请求中最高优先级的中断请求的信号。同时输入多个中断请求时预先设定。在地址寄存器7中,为了使多个中断处理的起始地址对应于可输入到优先级判断部6的多个中断请求,预先确定用于存储各个起始地址的位置71-7n。选择器8根据来自优先级判断部分6的用于指示中断请求之一的信号,将存在于存储相应中断处理的起始地址的位置处的地址选择性地输出到数据缓冲器9; COPYRIGHT:(C)1998 ,日本特许厅

著录项

  • 公开/公告号JPH10301792A

    专利类型

  • 公开/公告日1998-11-13

    原文格式PDF

  • 申请/专利权人 SANYO ELECTRIC CO LTD;

    申请/专利号JP19970106366

  • 发明设计人 TAKAHASHI MASAO;

    申请日1997-04-23

  • 分类号G06F9/46;

  • 国家 JP

  • 入库时间 2022-08-22 02:34:45

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