PHASE COMPARISON OPERATION CONTROL CIRCUIT FOR PLL CIRCUIT, AND THE PLL CIRCUIT

摘要

PROBLEM TO BE SOLVED: To stipulate proper phase comparison start timing and phase comparison end timing, even before a PLL feedback operation stabilizes as in a case that a power is supplied and an input signal is switched. SOLUTION: The maximum number of clocks from the front edge of a vertical synchronization period equivalent to a fly-back period is detected by a vertical counter 21 and fetched in a latch 23. A phase comparison control signal for inhibiting a comparison operation by a phase comparator 11 is outputted from a filp-flop 30 based on the maximum value. Since the start of a comparison operation inhibition period is stipulated based on the maximum value, a proper phase comparison control timing is stipulated, even before the PLL feedback operation has been stabilized.