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ASSOCIATIVE MEMORY AND ENCODING CIRCUIT TO BE APPLIED TO THE MEMORY

机译:关联存储器和编码电路将应用于该存储器

摘要

PROBLEM TO BE SOLVED: To facilitate the managing of invalid memory words by holding hit flags and empty flags in registers and successively outputting addresses of invalid memory words corresponding to the empty flags in accordance with a priority order. ;SOLUTION: Hit flags being the result after coincident retrievals among retieval data and respective memory words are performed are stored in registers 36a and logical sums for every subblock 32 are held in a subencoder 28a and the hit flags are made into active states in accordance with a priority order to be successively outputted and addresses of corresponding subblocks 32 are encoded to be outputted as addresses of memory words corresponding to respective hit flags together with memory words from a main encoder 12a. Moreover, registers 36b storing empty flags are provided and invalid memory words 34 corresponding to the priority order are managed similarly with hit flags. Furthermore, the encoding of addresses corresponding to either of the hit flags or the empty flags is decided in a timing control circuit 60a.;COPYRIGHT: (C)1999,JPO
机译:解决的问题:通过将命中标志和空标志保存在寄存器中并根据优先级顺序连续输出与空标志相对应的无效存储字的地址,来简化无效存储字的管理。 ;解决方案:命中标志是在检索数据和各个存储字中执行了同时检索之后的结果,被存储在寄存器36a中,每个子块32的逻辑和保存在子编码器28a中,并且命中标志根据优先顺序被依次输出,并且对应子块32的地址被编码以与来自主编码器12a的存储字一起被输出为与各个命中标志相对应的存储字的地址。此外,提供了存储空标志的寄存器36b,并且与命中标志类似地管理与优先级顺序相对应的无效存储字34。此外,在时序控制电路60a中确定与命中标志或空标志相对应的地址的编码。COPYRIGHT:(C)1999,JPO

著录项

  • 公开/公告号JPH1166867A

    专利类型

  • 公开/公告日1999-03-09

    原文格式PDF

  • 申请/专利权人 KAWASAKI STEEL CORP;

    申请/专利号JP19970228738

  • 发明设计人 YONEDA MASATO;

    申请日1997-08-26

  • 分类号G11C15/04;

  • 国家 JP

  • 入库时间 2022-08-22 02:31:15

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