首页> 外国专利> INTERNAL VOLTAGE SETTING CIRCUIT, SUBSTRATE VOLTAGE CLAMP CIRCUIT, SUBSTRATE BIAS GENERATING CIRCUIT, BOOSTING VOLTAGE CLAMP CIRCUIT, AND WORD LINE VOLTAGE GENERATING CIRCUIT

INTERNAL VOLTAGE SETTING CIRCUIT, SUBSTRATE VOLTAGE CLAMP CIRCUIT, SUBSTRATE BIAS GENERATING CIRCUIT, BOOSTING VOLTAGE CLAMP CIRCUIT, AND WORD LINE VOLTAGE GENERATING CIRCUIT

机译:内部电压设置电路,基底电压钳位电路,基底偏置产生电路,引导电压钳位电路和字线电压产生电路

摘要

PROBLEM TO BE SOLVED: To provide an internal voltage setting circuit which can perform an operation test in which operation guarantee margin is sufficiently secured independently of dispersion of a characteristic of a transistor caused by dispersion of a process. ;SOLUTION: Diode elements 100 are connected in series, and internal voltage V which is provided with the prescribed potential difference for input voltage Vin is set based on forward direction voltage drop. A switch element 101 is connected to the diode element 100, and increases and decreases the number of stages of the diode element 100 so that operation guarantee margin of internal voltage is enlarged based on a test mode signal T inputted at the time of operation test.;COPYRIGHT: (C)1999,JPO
机译:解决的问题:提供一种内部电压设置电路,该电路可以执行操作测试,其中与工艺分散引起的晶体管特性的分散无关,可以充分确保操作保证裕度。 ;解决方案:二极管元件100串联连接,并根据正向电压降设置内部电压V,该电压具有规定的输入电压Vin电位差。开关元件101连接到二极管元件100,并且增加和减少二极管元件100的级数,从而基于在操作测试时输入的测试模式信号T来增大内部电压的操作保证裕度。 ;版权:(C)1999,日本特许厅

著录项

  • 公开/公告号JPH1196796A

    专利类型

  • 公开/公告日1999-04-09

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;FUJITSU VLSI LTD;

    申请/专利号JP19970259068

  • 发明设计人 KIHARA HIROKI;FUJIKAWA MASAAKI;

    申请日1997-09-24

  • 分类号G11C29/00;G01R31/28;G11C11/407;G11C11/401;

  • 国家 JP

  • 入库时间 2022-08-22 02:30:43

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