Multi frame synchronization functional equipped error correction device

摘要

PURPOSE: To reduce the delay stages of a delay circuit for error correction. ;CONSTITUTION: The reception data inputted from a data input terminal 1 is written in a FIFO 5 and read out in a frame length unit. Multi-frame of (b) bits is read out from RAM 6 by one bit at the interval of frame length each time when the data is read out by one bit, latching b-1 bit excluding one bit of the oldest data and output 1 bit from the FIFO 5. The synchronization of the latched data (b) bit is detected and protected. When the synchronization of data read out from the FIFO 5 is established, an output gate section 11 outputs data to be inputted to the error correction circuit section 13. The data stored in the RAM 6 apart from one frame length is inputted to a delay circuit section 14. Decoding data with an estimated error bit pattern eliminated from an error correction circuit section 13 from a data output terminal 2 is outputted.;COPYRIGHT: (C)1993,JPO&Japio