首页> 外国专利> How to minimize the interruption of the pipeline processing of the hardware by means of software scheduling techniques during compilation

How to minimize the interruption of the pipeline processing of the hardware by means of software scheduling techniques during compilation

机译:如何在编译过程中通过软件调度技术最大程度地减少硬件流水线处理的中断

摘要

PURPOSE: To minimize source ware interruption within a compiled object code by sending an oldest instruction within a buffer to an object module and pushing the signal of a new instruction to the buffer. CONSTITUTION: When the instruction signal of each object code in a small consecutive group enters a scheduling process, the signal is assigned to a pair of attribute words developed from an instruction attribute table. Potential collision between a new instruction and an instruction in the buffer is confirmed in a first sub process by taking AND of the attribute word and the attribute word of another instruction. When there is no collision, an oldest instruction within the buffer is sent to an object module and the newest instruction is pushed into the buffer. When there is collision, whether a colliding instruction within the buffer can be moved or not within the buffer so as to minimize or remove the collision is decided and a second sub-process is executed so as to solve the collision.
机译:目的:通过将缓冲区中最旧的指令发送到目标模块并将新指令的信号推送到缓冲区,以最大程度地减少源代码在编译后的目标代码中的中断。组成:当连续的小组中每个目标代码的指令信号进入调度过程时,该信号将分配给从指令属性表中生成的一对属性字。在第一子过程中,通过取另一指令的属性字和属性字的“与”来确认新指令与缓冲区中的一条指令之间的潜在冲突。当没有冲突时,缓冲区中最旧的指令将发送到对象模块,最新指令将被推入缓冲区。当发生冲突时,确定是否可以在缓冲区内移动冲突指令以在缓冲区内移动以最小化或消除该冲突,并执行第二子处理以解决该冲突。

著录项

  • 公开/公告号JP2898105B2

    专利类型

  • 公开/公告日1999-05-31

    原文格式PDF

  • 申请/专利权人 INTERU CORP;

    申请/专利号JP19900405114

  • 发明设计人 SUTEIIBUN II KINGU;

    申请日1990-12-21

  • 分类号G06F9/38;G06F9/45;

  • 国家 JP

  • 入库时间 2022-08-22 02:30:29

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