PURPOSE: To reduce circuit scale by eliminating a conventionally required adder at the logarithm arithmetic circuit corresponding to values in fixed point expressions. ;CONSTITUTION: This logarithm arithmetic circuit is provided with a shift amount detector 1, shifter 2 for partitioning the value in the fixed point expression into an exponent part and a mantissa part, logarithmic transformation circuit for performing logarithmic transformation with '2' as a base to the value of the normalized mantissa part ≥0.5 and 1, and a decimal computing element 3 for outputting a value, for which '1' is added to a longarithmically transformed value outputted from the logarithmic transformation circuit, as a decimal part, and the shift amount detector 1 is provided with a function for outputting a value, for which '1' is subtracted from the value of the exponent part, as an integer part.;COPYRIGHT: (C)1994,JPO&Japio
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