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Gate impulse malfunction detection circuit null of electricity

机译:门脉冲故障检测电路无电

摘要

PURPOSE: To surely detect anomaly of gate pulse supplying conditions to the switching elements of a power converter by verifying, with logic circuits, that gate pulses are supplied to each one phase of upper and lower arms respectively without fail, and that they are not supplied to the upper and lower arms of the same phase simultaneously. ;CONSTITUTION: The title detecting circuit has an OR circuit 10 which finds the logical sum of gate pulses supplied to the Up-, Vp-, and Wp-phase switching elements of the upper arms of three-phase bridge connection, an OR circuit 12 which finds the logical sum of gate pulses supplied to the Un-, Vn-and Wn- phase switching elements of the lower arms, and an exclusive OR circuit 14 which finds the exclusive OR of the output signals of the OR circuits 10 and 12. Besides, it has AND circuits 16, 18, and 20 which find the logical products of Up and Un, Vp and Vn, and Wp and Wn respectively, and an OR circuit 22 which finds the logical sum of the respective output signals of the AND circuits 16, 18, and 20. Consequently, it becomes possible to detect phases failing gate pulses and malfunctions of a firing phase determining circuit for the switching elements.;COPYRIGHT: (C)1993,JPO&Japio
机译:目的:通过使用逻辑电路验证是否确实向上臂和下臂的每一相分别提供了门脉冲,并且没有提供门脉冲,从而确保检测到向功率转换器的开关元件提供门脉冲的条件异常。同时到同一相的上臂和下臂。 ;组成:标题检测电路具有一个或电路10,该逻辑电路找到提供给U p -,V p -和W 的门脉冲的逻辑和。三相电桥连接的上臂的p 个相开关元件,一个或电路12,它找到提供给U n -,V 的门脉冲的逻辑和下臂的n -和W n -相开关元件,以及异或电路14,其查找或电路10和12的输出信号的异或。它具有AND电路16、18和20,可找到U p 和U n ,V p 和V 的逻辑积n 和W p 和W n ,以及一个“或”电路22,该“或”电路22查找“与”电路16、18的各个输出信号的逻辑和。因此,可以检测出门脉冲失败的相位和开关元件的点火相位确定电路的故障。版权:(C)1993,JPO&Japio

著录项

  • 公开/公告号JP2829684B2

    专利类型

  • 公开/公告日1998-11-25

    原文格式PDF

  • 申请/专利权人 HITACHI SEISAKUSHO KK;

    申请/专利号JP19910341061

  • 发明设计人 OGAWA SHINICHI;KATO TETSUYA;

    申请日1991-12-24

  • 分类号H02M1/00;G05F1/10;

  • 国家 JP

  • 入库时间 2022-08-22 02:28:40

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