RESERVATION OVERRIDING NORMAL PRIORITIZATION OF MICROPROCESSORS IN MULTIPROCESSING COMPUTER SYSTEMS

摘要

the invention uses three programs of priority to determine which of several processing units receives the priority to become the master processor bus of a host bus in a multiprocessor system, and program for transferring control arbitration a master of the bus to another.each ranking priority class of elements, where a total of (n / 2) x (n + 1) bits of the priority controls the relative priority between each pair of elements. a component receives the highest priority in each of the n-1 bits of the priority associated with that element is.in the bus arbitration, teacher strength determines the moment at which the transfer of control of the host bus is such that it is governed by one of the programs are ranked in order of priority.the program provides for arbitration control bus eisa, regeneration of ram memory and direct memory access dma greater priority for units serving as bus masters and a bus master can interrupt the temporary bus master in neck so for a rewrite cache intervention cycle.the program also provides an arbitration processing pipeline of addresses, a transmission burst, split transactions aborted and cpu reservations, in the test of a cycle lock.the processing pipeline allows the next address bus to address control signal and the state before the start of the next phase of data transfer from the bus master.split transactions are applied to a central unit, a reading on the bus is assigned after the arbitration bus, host to another device without the need for a ru00e9arbitrage host bus to retrieve the data.the data is transmitted on the bus when it is inactive, the host, even when the bus is controlled by a host device.