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HIGH-SPEED, HIGH-CAPACITY, FAULT-TOLERANT, ERROR-CORRECTING STORAGE SYSTEM FOR BINARY COMPUTERS

机译:二进制计算机的高速,高容量,容错,纠错存储系统

摘要

the invention provides for the connection of a device to control access to a disk between a central computer unit (10), and a plurality of disk units (16) for a storage system with high speed, large capacity, and is insensitive to fault correction be their operating asynchronously.it also helps to improve the performance compared to previous versions.a number of control channels for the disc drive (46) are connected to the respective channels to drive units and control of data transfer to and from the units disc, each of the control channels of the disc drive includes a cache / buffer (48) and a u the microprocessor unit (50).a control circuit, and the interface unit (42) to interface with the host computer (10) and a central cache (54) is provided.a control logic circuit for controlling the transfer of data cached from the cache / buffer (48) of the plurality of channels (46) in order to drive units to the cache (54) and the cache (54) to the cache memory buffer (48). the plurality of channels (46) in order to drive units to and from the cache (54) to the computer 100"(10) through the control unit (42), and an interface. a central processing unit (60) manages the caching for data transfers to the data is not present in the cache (54) and by sending high level commands to the control channels (46) of the disc drive.a first bus (64) (data) is the interconnection of a plurality of buffer memories (48) antu00e9mu00e9moires / disk units, the control unit (42) and interface.and the cache (54) for the transfer of information between them, and a second bus (52) (information and orders) provides the interconnection between the components and a central processing unit (60) for the transfer of control and
机译:本发明提供了用于控制对中央计算机单元(10)和用于高速,大容量且对故障校正不敏感的存储系统的多个磁盘单元(16)之间的磁盘的访问的设备的连接。由于它们是异步运行的,因此与以前的版本相比,它还有助于提高性能。将磁盘驱动器(46)的许多控制通道连接到相应的通道上,以驱动单元并控制进出磁盘的数据传输,磁盘驱动器的每个控制通道都包括一个高速缓存器/缓冲器(48)和一个微处理器单元(50),一个控制电路,以及与主机(10)和中央处理器接口的接口单元(42)。提供了高速缓存(54)。控制逻辑电路,用于控制从多个通道(46)的高速缓存/缓冲器(48)高速缓存的数据的传输,以便将单元驱动到高速缓存(54)和高速缓存( 54)到高速缓冲存储器缓冲区(48)。多个通道(46),以便通过控制单元(42)驱动单元往返于高速缓存(54)和计算机(100)(10)之间的单元,以及接口。中央处理单元(60)管理该单元。通过将高级命令发送到磁盘驱动器的控制通道(46),在高速缓存(54)中不存在用于将数据传输到数据的高速缓存。第一总线(64)(数据)是多个缓冲存储器(48)ant u盘,控制单元(42)和接口以及用于在它们之间传递信息的高速缓存(54)和第二总线(52)(信息和命令)提供组件和中央处理单元(60)之间的互连,以传递控制权和

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