BARRIER SYNCHRONIZATION FOR DISTRIBUTED MEMORY MASSIVELY PARALLEL PROCESSING SYSTEMS

摘要

A barrier mechanism provides a low-latency method of synchronizing all or some of the processing elements (PEs) in a massively parallel processing system. The barrier mechanism is supported by one or more physical barrier synchronization circuits each receiving an input from every PE in the processing system. Each PE has an associated barrier synchronization register, in which each bit is used as an input to one of a plurality of logical barrier synchronisation circuits. The hardware supports both a conventional barrier function and an alternative eureka function. Each bit in the barrier synchronization registers can be programmed to perform as either barrier or eureka function, and all bits of the registers and each barrier synchronization circuits functions independently. Partitioning among PEs is accomplished by a barrier mask and interrupt register which enable certain of the bits in the barrier synchronization registers to a defined groups of PEs. Further partitioning is accomplished by providing bypass points in the physical barrier synchronization circuits to subdivide the physical barrier synchronization circuits into several types of PE barrier partitions of varying size and shape. The barrier mask and interrupt register and the bypass points are used in concert to accomplish flexible and scalable partitions corresponding to user-desired sizes and shapes with a latency several orders of magnitude faster than existing software implementations.