METHOD AND SYSTEM FOR IMPLEMENTING Cache Consistency Mechanism for Use in Non-Embedded Cache Memory Hierarchy

摘要

The present invention discloses a method and system for implementing a cache coherency mechanism to support a non-inclusive cache memory hierarchy in a data processing system. According to the method and system of the present invention, the memory hierarchy includes a primary cache memory, a secondary cache memory, and a main memory. The primary cache memory and the secondary cache memory are non-inclusive. Also, a first state bit and a second state bit are provided in the main cache with respect to each cache line of the main cache. In a preferred embodiment, the first state bit is set only if the corresponding cache line of the main cache memory is updated under a write-through mode, and the cache line also exists in the sub-cache memory The second status bit is set. The cache coherency between the main cache memory and the sub cache memory can be maintained by using the first state bit and the second state bit in the main cache memory.