Hardware-Managed Programmable Integrated / Split Caching Mechanisms for Commands and Data

摘要

In accordance with the present invention, a method is provided for allocating cache used by a processor of a computer system between at least two value classes, such as instructions and data. One logical device is connected to the cache to monitor the relative usage of the cache by each class and to select a predetermined cache usage rate by the class among a number of available rates, and cache blocks within the cache replace the cache that has been removed. Is removed using a cache replacement mechanism that restricts to a particular class of value classes based on a given cache usage ratio. The multi-bit function is provided to indicate how to limit the selected Victim to a given cache block, and the logic device selects a given cache usage rate by setting the multi-bit function. The cache replacement mechanism may be a least recently used replacement mechanism that has been modified to limit replacement of removed caches to a particular class of value classes based on a given cache usage rate. Multiple available ratios may include, for example, instruction / data cache block usage ratios of 1: 1, 1: 2, and 2: 1.