High-performance, high-bandwidth memory bus utilizing synchronous dynamic RAMs

摘要

The present invention provides a high performance, high bandwidth memory bus structure and module. The module includes standard synchronous DRAM (SDRAM) chips and may be a card with reduced latency and pin count. The four bus pins separate input commands from the data to establish parallel system operations. By maintaining packetized transactions, independent memory operations can be improved over normal SDRAM operations. In this structure, the bus is divided into commands and data inputs separated from the output data.