ALARM AND RESYNCHRONIZED CLOCK GENERATOR IN DAMA-SCPC

摘要

The alarm and synchronous recovery clock generating device according to the present invention receives an input condition signal from each part of the system and generates a clock enable signal (ENRCK1, ENRCK2) and an alarm enable signal (EN-FAIL-1, EN-) when a predetermined condition is generated. Enable signal generating means for generating FAIL-2); A line driver / receiver 22 for receiving a clock extracted from the outside and outputting a synchronized recovery clock when a clock enable signal is input from the enable signal generating means; And a three-phase buffer 23 that receives and outputs an alarm signal controlled / monitored from the outside when an alarm enable signal is input from the enable signal generating means, and monitors the operation state of the clock and the operation of the board mounted in the slot. And controllable circuits can be simply implemented using programmable elements.