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Packetized basic bit sequence reconstruction device for the interface of encoder and multiplexing period
Packetized basic bit sequence reconstruction device for the interface of encoder and multiplexing period
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机译:编码器和复用周期接口的分组基本位序列重构装置
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摘要
1. TECHNICAL FIELD OF THE INVENTION;The present invention relates to a packetized basic bit string reconstruction apparatus.;2. The technical problem to be solved by the invention;The present invention provides an interface of an encoder and a multiplexing period for correcting an error generated by comparing basic bit string clock reference (ESCR) information included in a header of a packetized basic bit string with system timing clock information in a multiplexer at a specific period. To provide a packetization basic bit string reconstruction device.;3. Summary of Solution of the Invention;The present invention includes a detector for detecting basic bit string clock reference information from an input packetized basic bit string; A clock generator for generating time stamp information; A comparator for comparing the input basic bit string clock reference information and time stamp information and outputting an error value thereof; And a reconstruction unit for reconstructing the packetized basic bit string by correcting the reproduction and decoding timestamp of the input packetized basic bit string by the error value.;4. Important uses of the invention;The present invention is used in an encoding device and the like.
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