The write-accept circuit 1 comprises a write detector 2 and a bistable element 3. The write detector of the circuit 1 according to the invention comprises two switch elements 21, 22 or 23, 24 connected in series, unlike the write detector of the prior art comprising 10 switch elements. This record detector 2 also has two record inputs 4 and 5 and two complementary inputs 11 and 12 and an acknowledgment output 6 coupled to the control input of the switch element and an acknowledgment output 6 to the switch. It is formed by the connecting portion of the element. The write signal on the write inputs 4, 5 encodes a 1-bit variable according to the double-rail encoding method using four-phase handshake signaling on the write signal.;The two write inputs of the record detector 2 also form two inputs of the bistable element 3. The bistable element 3 is connected to the recording detector 2 to excite the acknowledgment output 6 via the complementary input of the recording detector 2 in response to the recording signal on one of the two recording inputs 4, 5. It has two outputs 7, 8 coupled alternately to the complementary input. The acknowledgment signal on acknowledgment output 6 indicates that the write signal has been processed by circuit 1 and now the write signal is allowed to change the value.
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