SYNCHRONOUS DIGITAL SIGNAL TO ASYNCHRONOUS DIGITAL SIGNAL DESYNCHRONIZER

摘要

An improvement in jitter performance is realized with an asynchronous device that obtains an asynchronous digital signal, such as a DS3 signal, from a received synchronous digital signal, such as a SONET STS-1 signal. The improvement in jitter performance is realized by using a unique adjustable bit leakage device with digital phase locked loops and synchronous elastic memory. Estimation of the bit leakage period is made through adjustment based on the period between successive point adjustment sequences of the received signal, i.e., the STS-1 signal. In one embodiment, the bit leakage period estimation is obtained by utilizing the moving average of the period between pointer adjustments. Desired bit leakage is implemented by utilizing accumulators and comparators that respond to received pointer adjustments and estimated bit leakage periods. The output count of the accumulator is supplied to the comparator in accordance with the write address of the elastic storage unit. The leak bits are fed to the phase calibration loop as an output of the comparator one at a time, which generates a gentle read clock in the elastic memory.