BITSTREAM SYNTAX PARSING CONTROL CIRCUIT IN VIDEO DECODER

摘要

The present disclosure relates to a bit stream parsing control circuit of a video decoder capable of parsing bit stream data input at high speed without any external hardware configuration in accordance with the MP @ HL specification which is a standard specification of HDTV proposed in MPEG 2. The control circuit of the present invention includes a comparator for receiving bitstream data of a predetermined unit and providing a basis for analyzing a state corresponding to a syntax of the standard, A variable length call table unit for selecting a value of a call and some bit data of the data to be used for the next state analysis and outputting the length and the contents of the variable length call; A state determination unit for receiving a state corresponding to the contents and the current syntax and analyzing a state corresponding to the following statement and outputting a value or a control signal to be shifted according to the state, and a storage unit for storing the contents of the variable- A value to be shifted by a desired bit is received from the status determination section, And by aligning them into bytes according to the standard it is composed of an output shift value decision. Therefore, the present invention provides an effect of performing decoding by bit stream parsing in a video decoder of MPEG 2 standard at high speed without any external hardware configuration.