FREQUENCY AND PHASE COMPARATOR IN CMOS PLL

摘要

The present invention relates to a frequency phase comparator of a phase locked loop (PLL). In the past, a PLL using a frequency phase comparator has been able to operate in a maximum 400 MHz band in a 0.8 μm CMOS process, In the band 800 to 900 MHz, since the PLL using a 0.8 μm CMOS process can not be realized, a PLL of a very high frequency band has been configured and used by using a compound semiconductor (GaAs), a birol or a BiCMOS. In this case, since it is composed of 52 transistors, there is a problem in that the loss is large in cost, density, and power consumption than in the CMOS process, and since the frequency phase comparator operates by edge triggering, There is a problem. Accordingly, the present invention provides an output control apparatus including: an output control unit 100 having a clear transistor for comparing an input level and an output level of a voltage controlled oscillator and determining whether to output the output level; and an output control unit 100 for buffering the output of the output control unit 100, Down signal buffers 200 and 300 for enhancing a signal can be realized with only six transistors to achieve high integration, low power consumption, and high-speed operation, and to overcome the limit of frequency that can detect a phase error It is possible to operate in the 1 GHz band, so that it can be applied to mobile communication and the like.