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Counter with error detection and error correction.
Counter with error detection and error correction.
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机译:带有错误检测和错误纠正的计数器。
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摘要
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摘要
A decoded counter employing a shift register and a zero-detect circuit has the ability of returning to a correct state within a limited number of clock cycles if, by accidental reasons, an invalid state is assumed by the counter. One of the flip-flops is provided with synchronous set while all the other flip-flops of the shift register are provided with synchronous reset. The output of the last flip-flop of the register drives a single set-reset line common to all the flip-flops and the pull-up line of the zero-detect circuit is connected to the input of the first flip-flop of the register. Optionally, one of the flip-flops may be provided with asynchronous set and the others with an asynchronous reset, for initializing the counter in a certain state through a single clear-load line.
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