Circuit for carrying out the euclid algorithm in the decoding arithmetic codes

摘要

An object of the present invention is to reduce the circuit size without damage to the high speed.; In the configuration of the present invention registers (21 to 28) there is stored each continue elongation ROM (S ₀ ~ S _7), resistors (31-38) is stored in the coefficients of the polynomial pije. Multipliers (51-57) and is multiplied by a coefficient of the polynomial pije the output Q (X), an adder (41-47) is the rest by multiplying the outputs of the multipliers (51-57) to the output of registers (21-27) and outputs it to the next stage. Further, the register (21 to 28) output is stored in the register (21 to 28) each of which is stored in registers (31-38), the output of the registers (31-38), through a switch (60-67) of the data and the exchange, it is possible to reduce the circuit size. As yet a separate embodiment, the modified syndrome generating / Euclid's divider 3 for the syndrome generation circuit (1) is the calculated syndrome and the erasure position generating circuit 2 is modified syndrome at the same time to generate a modified syndromes from the erasure locations coefficient obtained used to calculate the error value polynomial by performing the Euclidean division of. Erasure locator polynomial generating / Euclid optimization operation for the circuit 4 generates an erasure position polynomial from the erasure locations coefficient, and further by using the share of the erasure locator polynomial and an error locator polynomial obtained in the Euclidean division. Give the error position polynomial and error value polynomial to the chain search circuit 6 to obtain an error location and an error value, corrects the error of wear may in the correction processor 7. Obtain a modified syndrome using the Euclid's divider, to obtain the erasure locator polynomial using the optimization computation circuit and, thereby reducing the circuit scale by sharing a circuit.