Interface device for XT/AT system devices on high speed local bus

摘要

A host bus interface device is provided for interfacing a processor coupled to a host bus to XT/AT legacy I/O devices and a high speed bus. The legacy I/O devices include an interrupt controller, timer/counter and a real time clock. The host bus interface includes a host controller coupled between the host bus and the high speed bus, with the interrupt controller, the timer/counter and the real time clock coupled to the host controller. The host controller is configured to provide an interface between the processor coupled to the host bus and the interrupt controller, the timer/counter, the real time clock device and the high speed bus. The novel host bus interface device has the advantage of improving system performance of an XT/AT compatible personal computer by reducing access latency of the processor to the XT/AT legacy I/O devices.