Microprocessor using combined actual and speculative branch history prediction

摘要

A pipelined microprocessor (10) and system (2) incorporating the same, utilizing combined actual branch history and speculative branch history to predict branches, is disclosed. The microprocessor (10) includes a branch target buffer, or BTB, (56) having a plurality of entries (63) that are associated with previously branching instructions. Each entry (63) has a tag field (TAG) for storing an identifier for its branching instruction based upon the logical address therefore, and a target field (TARGET) for storing the target address for the branching instruction if the branch is taken. Each entry (63) also includes a branch history field (BH), the most-recent bits of which are applied to a pattern history table, or PHT, (53) as an index thereto to retrieve a prediction for the branch. A count field (CT) is also provided with each entry (63), to count the number of positions in the branch history field (BH) that correspond to speculative history, such as may arise in closely- packed programs where multiple instances of the branching instruction are encountered before resolution of an earlier instance. Upon resolution of the branching instruction, correct predictions are indicated by decrementing the count field (CT) for its entry. Mispredictions are reflected in the BTB (56) by the corresponding entry having its count field (CT) reset to reflect that no speculative history remains, by shifting the branch history field (BH) downward, and by including the actual result of the mispredicted branch therein. This arrangement allows more actual branch history to be used in predicting the next instance of the branching instruction, while maintaining the storage requirements of the BTB (56) relatively low.