Deadlock avoidance mechanism for virtual bus distributed hardware simulation

摘要

To simulate a bus of a circuit, a number of virtual bus stubs ("VBSs") each post simulated bus signals as a single step and execution of the simulation system which includes such a VBS continues. As a subsequent, separate step, the VBS substantially immediately thereafter reaps a resolved simulated bus state. Synchronization in such a system is achieved by grouping into zones all VBSs which collectively represent the simulated state of a single bus. Each VBS has one of four states, namely, reap running, reap stopped, post running, post stopped. When a VBS posts, it is determined whether any other VBS of the same zone has yet to reap a previously resolved simulated bus state. If such a VBS exists, the posting VBS moves from reap running state to a post stopped state and execution of the simulation system containing the posting VBS is suspended until the last VBS of a zone reaps the previously resolved simulated bus state. Otherwise, if all VBSs of the same zone have reaped the previously resolved simulated bus state, the posting VBS moves from a reap running state to a post running state and execution of the simulation system containing the posting VBS continues. When a VBS reaps, it is determined whether any other VBS of the same zone has yet to post simulated bus signals for the current resolution of the simulated bus state. If such a VBS exists, the reaping VBS moves from post running state to a reap stopped state and execution of the simulation system containing the reaping VBS is suspended until the last VBS of a zone posts simulated bus signals for the current resolution of the simulated bus state. Otherwise, if all VBSs of the same zone have reaped simulated bus signals for the current resolution of the simulated bus state, the reaping VBS moves from a post running state to a reap running state and execution of the simulation system containing the reaping VBS continues.