Clock generator for generating complementary clock signals with minimal time differences

摘要

An improved complementary-type clock generator minimizes the time difference between a normal clock signal and an inverted clock signal. The clock generator includes an inverting unit for outputting Vcc- Vtn and Vss+Vtp level voltage by pulling up and pulling down the source voltage and ground voltage in accordance with an externally applied clock signal, and a first buffer for outputting Vcc-Vtn and Vss+Vtp level voltages by pulling up and pulling down the source voltage and ground voltage in accordance with an externally applied clock signal. A level converting unit receives the Vcc-Vtn and Vss+Vtp level voltages and second and third buffers invert the outputs of the level converting unit for outputting a normal clock signal and an inverted clock signal.