首页>
外国专利>
Memory design which facilitates incremental fetch and store requests off applied base address requests
Memory design which facilitates incremental fetch and store requests off applied base address requests
展开▼
机译:内存设计可促进增量提取和存储已应用的基地址请求中的请求
展开▼
页面导航
摘要
著录项
相似文献
摘要
A memory design which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built into the memory's decoding circuitry. The introduction of an internal address generation facility simplifies extraneous control of typical requesters built into a memory system. The memory design also reduces power consumed by requests which exploit the memory's internal address generation facility. Power consumption is further reduced while maintaining memory access times by selectively gating data bits vital to the memory's logic flow at an earlier stage in the memory when the gating or steering address bits are known in advance of the data arriving to that stage.
展开▼