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Relay-race FLL/PLL high-speed timing acquisition device

机译:继电器竞赛FLL / PLL高速时序采集设备

摘要

A relay-race FLL/PLL high-speed timing acquisition device according to the invention comprises a transition detector, a voltage controlled oscillator, a loop filter of PLL, a first lowpass filter, a 90° phase shifter, a second lowpass filter, and a plurality of multipliers. In addition, this relay-race FLL/PLL high-speed timing acquisition device is characterized by further comprising a frequency delimiter which includes a highpass filter coupled to a first circuit, a second circuit coupled to the highpass filter, a third lowpass filter coupled to the second circuit, a Schmitt inverter coupled to the third lowpass filter, and a switch member coupled to the Schmitt inverter. The relay-race FLL/PLL high-speed timing acquisition device can obtain stable and high speed timing acquisition by means of the frequency delimiter.
机译:根据本发明的中继竞赛FLL / PLL高速定时获取装置包括转换检测器,压控振荡器,PLL的环路滤波器,第一低通滤波器,90°移相器,第二低通滤波器,以及多个乘法器。另外,该继电器竞赛FLL / PLL高速定时获取装置的特征在于,进一步包括分频器,该分频器包括耦合至第一电路的高通滤波器,耦合至高通滤波器的第二电路,耦合至第一电路的第三低通滤波器。第二电路,耦合到第三低通滤波器的施密特逆变器,和耦合到施密特逆变器的开关构件。继电器竞赛FLL / PLL高速定时采集设备可以通过分频器获得稳定,高速的定时采集。

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