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Floating point NaN comparison

机译:floating point NaN comparison

摘要

A circuit for comparing and selecting NaN inputs is disclosed. Each NaN input is transformed by appending a sign bit to the end of a significand. In one particular embodiment, the inverse of the sign bit is appended to the significand. Accordingly, the transformed inputs include the significand and a least significant bit which indicates whether the input was positive or negative. The transformed inputs are compared by a comparator circuit such as a carry tree. An output of the carry tree controls a multiplexer which selects a first input if a first transformed input is greater than or equal to a second transformed input, and selects a second input if the second transformed input is greater than the first transformed input.
机译:公开了一种用于比较和选择NaN输入的电路。通过将符号位附加到有效数的末尾来转换每个NaN输入。在一特定实施例中,将符号位的倒数附加到有效位。因此,变换后的输入包括有效位和最低有效位,其指示输入是正还是负。转换后的输入通过比较器电路(例如进位树)进行比较。进位树的输出控制多路复用器,如果第一变换后的输入大于或等于第二变换后的输入,则选择多路复用器,如果第二变换后的输入大于第一变换后的输入,则选择第二输入。

著录项

  • 公开/公告号US5931943A

    专利类型

  • 公开/公告日1999-08-03

    原文格式PDF

  • 申请/专利权人 ADVANCED MICRO DEVICES INC.;

    申请/专利号US19970955287

  • 发明设计人 HOLGER ORUP;

    申请日1997-10-21

  • 分类号G06F9/302;

  • 国家 US

  • 入库时间 2022-08-22 02:07:41

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