PLL frequency synthesizer with K multiplication in addition to division for subtraction of phase noise

摘要

A frequency synthesizer is supplied with an input signal of frequency . function..sub.i to provide an output signal ƒ.sub.o where . function..sub.o=ƒ.sub.i M/N and M and N are integers. The input signal is first applied to a divider circuit for division by M/K where K is an integer and the resultant is applied as inputs to a phase locked loop. The phase locked loop includes a ring oscillator of frequency . function..sub.i N/M, a frequency multiplier circuit for multiplying by K, and a frequency divider circuit for dividing by N. The ring oscillator uses a combinational logic circuit that combines the outputs of four differential delay elements to produce a frequency multiplication of four.