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Computer implemented method for estimating fabrication yield for semiconductor integrated circuit including memory blocks with redundant rows and/or columns
Computer implemented method for estimating fabrication yield for semiconductor integrated circuit including memory blocks with redundant rows and/or columns
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机译:用于估计包括具有冗余行和/或列的存储块的半导体集成电路的制造成品率的计算机实现的方法
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摘要
A computer is used to estimate a fabrication yield for a semiconductor product under design which includes a plurality of integrated circuit dies, each of which includes a memory cache having a predetermined redundancy scheme in the form of redundant rows and/or columns. A bitmap failure analysis of an existing semiconductor product including a plurality of integrated circuit dies having bitmap failure modes that are comparable to those of the product being designed is performed to obtain a number of failed caches. An observed repair rate is computed as a ratio of a number of the failed caches that can be repaired by the predetermined redundancy scheme to the number of failed caches. A model repair rate for the predetermined redundancy scheme which approximates the observed repair rate is computed using a multiple Poisson model including computed average numbers &lgr; of failures for the failure modes respectively. The numbers &lgr; are optimized by minimizing a least squares difference between the observed repair rates and the model repair rates. The fabrication yield is computed as a predetermined function of the model repair rate including scale factor(s) for the circuit on the wafer being designed. The method can be used to select a redundancy scheme for the wafer by computing fabrication yields for a plurality of candidate redundancy schemes, and selecting the redundancy scheme which has the highest return for additional test, manufacturing and design investment.
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