Non-symmetric radial and non-symmetric pruned radial interpolation

摘要

New interpolation techniques allow improved efficiency and speed in performing color space conversions. A radial interpolation technique accomplishes an interpolation by generating successive subcubes. A value of a vertex of the final subcube generated is used as the result of the interpolation. Subcubes are generated by averaging a selected vertex value with the vertex values of each of the remaining vertices. A pruned radial interpolation technique employs a subset of the vertex values of the initially selected cube to generate the result of the interpolation, thereby improving upon the efficiency of the radial interpolation. A tetrahedral interpolation technique accomplishes an interpolation by generating successive subcubes. A value of a vertex of the final subcube generated is used as the result of the interpolation. Subcubes are generated by applying a mathmatical relationship which allows computation of subcube vertex values through a series of logical AND, logical OR and averaging operations. A pruned tetrahedral interpolation technique employs a subset of the vertex values of the initially selected cube to generate the result of the interpolation, thereby improving upon the efficiency of the tetrahedral interpolation. A common hardware implementation of pruned radial interpolation and pruned tetrahedral interpolation uses the common hardware structure of the two techniques with multiplexing of the input vertex values to allow performance of either a pruned radial interpolation or a pruned tetrahedral interpolation. Non-symmetric pruned radial and Non-symmetric pruned tetrahedral interpolation permit interpolation using interpolation data values distributed throughout the color space with a resolution that varies according to characteristics of the color space. Multiplexing of the interpolation data values to the non-symmetric pruned radial interpolation hardware and to the non-symmetric pruned tetrahedral interpolation hardware allows for a common hardware implementation.