Superscalar microprocessor stack structure for judging validity of predicted subroutine return addresses

摘要

A return stack is described which stores return addresses associated with subroutine call instructions along with an ESP register value associated with the subroutine call instructions in a stack-type structure. During clock cycles that a return instruction is detected by a decode unit, the decode unit forwards an ESP register value associated with the return instruction to the return stack along with an indication of the return instruction detection. The return stack compares the forwarded ESP register value to the ESP register value stored on the top of the stack. If the values compare equal, then the value stored on the top of the stack may be the correct prediction address for this return instruction and is popped from the top of the stack. When the return stack detects an inequality between the two aforementioned ESP values, the return stack does not pop the top of the stack. The return stack may achieve a correct prediction rate substantially similar to the correct prediction rate in the absence of fake return instructions, even if fake return instructions are encountered.