Precise, low-jitter fractional divider using counter of rotating clock phases

摘要

A fractional divider divides an input by a non-whole number M. N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock increments a counter that counts to the integer part M. The selected clock also increments a rotational state machine. The rotational state machine makes the mux select a different one of the multi-phase clocks for the first N clocks so that the phase of the selected clock is rotated for N cycles. When multi-phase clocks having slightly higher delays are chosen, the selected clock's period increases, adding a fraction. When multi-phase clocks having slightly smaller delays are chosen, the selected clock's period is reduced, effectively subtracting a fraction. The delay line is part of a delay-locked loop that compares the phase of the last multi-phase clock to the input clock. Any phase difference charges a loop filter and changes an adjustment voltage. The adjustment voltage changes the delays in the delay line so that the sum of all delays in the delay line matches the clock period. Since smaller count values can be used when fractional rather than whole- number divisors are used, phase comparisons in a PLL are increased, reducing jitter and smoothing the output.