Speed-enhancing comparator with cascaded inventors

摘要

A speed-enhancing comparator with cascaded inverters is disclosed. The comparator comprises: a first capacitor, a first inverter, and a first switch, wherein the first switch and the first inverter are connected in parallel, and a first terminal of the first capacitor is coupled to an input terminal of the first inverter; a first input switch and a second input switch, wherein input terminals of the first and second input switches are coupled to an input voltage and a reference voltage respectively, and both output terminals of the first and second input switches are coupled to a second terminal of the first capacitor; a second inverter, a second switch, and a third switch, wherein the second inverter and the third switch are connected in series and then connected in parallel with the second switch, and an output terminal of the first inverter is coupled to an input terminal of the second inverter; and a second capacitor, a third inverter, and a fourth switch, wherein the fourth switch and third inverter are connected in parallel, and a first terminal of the second capacitor is coupled to an input terminal of the third inverter, and a second terminal of the second capacitor is coupled to both output terminals of the second and third switches. The first to fourth switches and the first and second input switches carry out on/off operations, whereby the third inverter outputs a comparing result of the input voltage and the reference voltage.