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Method and system for buffering condition code data in a data processing system having out-of-order and speculative instruction execution

机译:在具有乱序和推测性指令执行的数据处理系统中缓冲条件代码数据的方法和系统

摘要

In response to dispatching a condition register modifying instruction to an execution unit, a condition register rename buffer is associated with such a condition register modifying instruction. The instruction is then executed in the execution unit. Following the execution of the condition register modifying instruction, condition register data is set in the condition register rename buffer to reflect the result of such instruction execution. Additionally, an indicator is set to indicate the condition register data is valid. At the time for completing the condition register modifying instruction, the condition register data is transferred from the condition register rename buffer to the architected condition register, thereby permitting condition register modifying instructions to be dispatched, executed, and finished before the condition register is available to complete each condition register modifying instruction.
机译:响应于将条件寄存器修改指令分派给执行单元,条件寄存器重命名缓冲器与这种条件寄存器修改指令相关联。然后在执行单元中执行指令。在执行条件寄存器修改指令之后,在条件寄存器重命名缓冲器中设置条件寄存器数据以反映该指令执行的结果。另外,设置指示器以指示条件寄存器数据有效。在完成条件寄存器修改指令时,将条件寄存器数据从条件寄存器重命名缓冲区传输到架构条件寄存器,从而允许在条件寄存器可用于之前分配,执行和完成条件寄存器修改指令。完成每个条件寄存器修改指令。

著录项

  • 公开/公告号US5974240A

    专利类型

  • 公开/公告日1999-10-26

    原文格式PDF

  • 申请/专利权人 INTERNATIONAL BUSINESS MACHINES CORPORATION;

    申请/专利号US19950480999

  • 发明设计人 KIN SHING CHAN;

    申请日1995-06-07

  • 分类号G06F9/38;

  • 国家 US

  • 入库时间 2022-08-22 02:06:54

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