Delay calculation method of the logic circuit, delay data calculation method of the delay calculation apparatus and delay library

摘要

PROBLEM TO BE SOLVED: To surely obtain delay time by easily and analytically calculating the power supply voltage dependency of delay time of a logic circuit. ;SOLUTION: In a delay power supply coefficient determining process S03, the drain saturated current Idspi of a p-channel MOS FET is calculated based on prescribed operation power supply data 15 and saturated current parameters 16 such as the moving distance of a carrier and the thickness of an oxidized film based on the data 15 and then the ratio of the current Idspi to the drain saturated current Idsp0 of the p-channel MOS FET at the time of impressing reference power supply voltage Vdd0 is calculated to determine a delay power supply coefficient Kv at the time of impressing operation power supply voltage Vddi. In an effective delay calculation process S04, an effective delay calculation means multiples delay time at the time of impressing the reference power supply voltage Vdd0 calculated by a delay calculation means by the delay power supply coefficient Kv calculated by a delay power supply coefficient determining means to determine the delay time at the operation power supply voltage Vddi.;COPYRIGHT: (C)1999,JPO