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Layout compaction equipment and layout compaction method

机译:布局压实设备和布局压实方法

摘要

A layout compaction method adapted to be embodied in computer program product and adapted for compacting a circuit layout having a plurality of layers on which moving objects form layer patterns, wherein the moving objects comprising components and wires. The method assumes a graph problem under condition which prevent the compacted result from violation of the design rule, and then, solves the graph problem to determine a moving order, a moving direction, and a moving distance of each component for moving the components to thereby perform the compacting the circuit layout. After that, the method moves each component according to the moving order, the moving direction and the moving distance to obtain a compacted circuit layout.
机译:一种布局压缩方法,适于在计算机程序产品中实现并且适于压缩具有多个层的电路布局,在该多个层上,移动物体形成了层图案,其中,移动物体包括部件和导线。该方法在防止紧缩结果违反设计规则的条件下假设图形问题,然后解决该图形问题以确定用于使各部件移动的各部件的移动顺序,移动方向和移动距离。执行紧凑的电路布局。此后,该方法根据移动顺序,移动方向和移动距离移动每个组件,以获得紧凑的电路布局。

著录项

  • 公开/公告号JP3077757B2

    专利类型

  • 公开/公告日2000-08-14

    原文格式PDF

  • 申请/专利权人 日本電気株式会社;

    申请/专利号JP19990025310

  • 发明设计人 菊地 秀雄;長野 圭治;秋元 豊;

    申请日1999-02-02

  • 分类号G06F17/50;H01L21/82;

  • 国家 JP

  • 入库时间 2022-08-22 02:04:55

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