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MASTERLESS SERIAL BUS OCCUPANCY CONTROL METHOD AND DISTRIBUTED CONTROL SYSTEM

机译:串行总线无故障主机控制方法及分布式控制系统

摘要

PROBLEM TO BE SOLVED: To efficiently perform cyclic data transfer, while considering the transmission data amount of respective programmable controllers (PC).;SOLUTION: Based on the responsiveness of a system or data amount of respective PC, edition information such as the total number of time slots, allocated time slot number and time slot time is set from an engineering tool to a transmission timing determining device 27 of each PC 1. When reception is interrupted, an MPU 24 compares the transmission source time slot number of a received data frame with its own time slot number and when it is its turn, transmission processing is performed by activating the time slot timer of a time measuring device 25. At that time, the number of continuous time slot numbers allocated to the MPU itself is managed and for transmission time after the second serial number, each time of transmission processing of the preceding number, the time slot timer is activated and determined synchronously with time slot time. The number of time slots to be allocated to each PC can be set corresponding to the transmission data amount, and the transmission efficiency of a serial bus is improved.;COPYRIGHT: (C)2000,JPO
机译:解决的问题:在考虑相应的可编程控制器(PC)的传输数据量的同时,要有效地执行循环数据传输;解决方案:基于系统的响应速度或相应的PC的数据量,应发布版本信息,例如总数从工程工具向每个PC 1的发送定时确定装置27设置时隙的数量,分配的时隙编号和时隙时间。当接收中断时,MPU 24比较接收到的数据帧的发送源时隙编号。利用它自己的时隙号,并且当轮到它时,通过激活时间测量装置25的时隙定时器来执行发送处理。在那时,管理分配给MPU本身的连续时隙号的数目,并且第二个序列号之后的传输时间,在前一个序列号的每次传输处理中,激活时隙计时器并与tim同步确定插槽时间。可以根据传输数据量设置要分配给每个PC的时隙数,并提高了串行总线的传输效率。;版权所有:(C)2000,JPO

著录项

  • 公开/公告号JP2000172658A

    专利类型

  • 公开/公告日2000-06-23

    原文格式PDF

  • 申请/专利权人 HITACHI LTD;

    申请/专利号JP19980343861

  • 发明设计人 TAKAHASHI NARIHARU;

    申请日1998-12-03

  • 分类号G06F15/177;G06F13/368;G06F15/173;H04L12/40;

  • 国家 JP

  • 入库时间 2022-08-22 02:01:17

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