PROCESSOR AND INSTRUCTION TAKE-OUT METHOD FOR SELECTING ONE OF PLURAL TAKE-OUT ADDRESSES GENERATED IN PARALLEL TO GENERATE MEMORY REQUEST

摘要

PROBLEM TO BE SOLVED: To shorten an instruction take-out wait time by generating a target address and sequential addresses and the a select signal in parallel. ;SOLUTION: A decoder 40 determines the target address according to an instruction in a take-out window 38. Further, an adder 48 calculates sequential take-out addresses from the address of the final instruction in an instruction queue 30 and the length of the final instruction. Then priority order logic 42 decides whether or not an unprocessed branch instruction is included in the take-out window 38. When it is decided that no unprocessed branch instruction is included, the priority order logic 41 selects the sequential take-out addresses. A multiplexer 50 selects at least one of decoded input addresses as a memory request address in response to the select signal 52. Then when the solution that the target address is correct is obtained, instructions in a sequential path can be discarded.;COPYRIGHT: (C)2000,JPO